SDRAM (Synchronous DRAM) has become the memory standard in many\ndigital system designs, because of low price and high read/write speed. In this\npaper, Based on the analysis of the working principle and characteristics of\nSDRAM, an SDRAM controller design method is proposed based on field programmable\nlogic gate array FPGA. In order to reduce resource consumption\nand increase the read and write speed of SDRAM, the performance control of\nSDRAM is further optimized. We designed SDRAM controller by using Verilog\nHDL and Altera Quartus II 14.1 software, and simulated about this design\nwith Model Sim-Altera 10.3c software. Then we verified this design by\nusing Cyclone V 5CSEMA5F31C6 FPGA in DE1-SoC development board.\nThe verification results show that the SDRAM is initialized successfully, the\ninput and output data are completely consistent, and it has stable refresh and\nread and write functions. The SDRAM controller design meets the requirements.
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